Method of providing lower contact resistance in MOS transistor structures

ABSTRACT

Germanium is used to significantly enhance the drift mobilities of minority carriers in the channels of N-channel and P-channel metal-oxide-semiconductor (MOS) transistors with silicon substrates. Germanium processing is also used to enhance the source/drain contact conductance for MOS devices. Methods are disclosed for forming the germanium-rich interfacial layer utilizing a germanium implant and wet oxidation or growing a silicon-germanium alloy by molecular beam epitaxy.

BACKGROUND OF THE INVENTION

1. Field of the Invention

In accordance with the present invention, germanium is used to enhancethe performance of silicon-based semiconductor devices. Morespecifically, germanium is used to create a germanium-rich layer at thesilicon surface to provide lower contact resistance in the source anddrain regions of MOS transistors.

2. Discussion of the Prior Art

The inherent properties of germanium that are capitalized upon inaccordance with the present invention are as follows. First, it is wellknown that at normal integrated circuit operating temperatures (approx.27° C.), the drift mobility of electrons and holes in germanium exceedsthe drift mobility in silicon by a factor of from 3-10. As discussed byS. N. Sze, "Physics of Semiconductor Devices", John Wiley & Sons, NewYork, 1981, Second Edition, page 29, the actual drift mobility factor isa function of impurity concentration. Second, the diffusion of siliconthrough germanium is faster than the diffusion of germanium throughsilicon. Third, the intrinsic resistivity of germanium (47Ω·cm) is fourorders of magnitude smaller than the intrinsic resistivity of silicon.Fourth, as discussed by A. R. Srivatsa et al, "Nature of Interfaces andOxidation Processes In Germanium Implanted Silicon," Journal of AppliedPhysics, 65:4028 (1989), the wet oxidation of silicon with a germaniumimplant present can be used to form epitaxial layers of germanium. Asdisclosed by D. Fathy et al, "Formation of Epitaxial Layers of Germaniumon Silicon Substrates by Germanium Implantation and Oxidation", AppliedPhysics Letter 51:1337 (1987), these germanium epitaxial layers can beformed without forming germanium oxide layers.

SUMMARY OF THE INVENTION

The phenomenon that wet oxidation of silicon wafers implanted with highdose, low energy germanium results in segregation of the germanium inthe silicon along with formation of an almost pure germanium layer inthe interfacial region is used to create MOS transistor structures withlower contact resistance in the source and drain regions.

Alternatively, an epitaxial layer of silicon-germanium alloy of thedesired germanium purity may be formed in the interfacial region tolower contact resistance.

A better understanding of the features and advantages of the presentinvention will be obtained by reference to the following detaileddescription of the invention and accompanying drawings which set forthan illustrative embodiment in which the principles of the invention areutilized.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A-1C are cross-sectional drawings illustrating introduction of agermanium layer into the channel region of an MOS device .

FIGS. 2A-2B are cross-sectional drawings illustrating introduction of agermanium layer into the source/drain regions of an MOS device inaccordance with the present invention.

FIGS. 3A-3B are cross-sectional drawings illustrating an alternativemethod of introducing a germanium layer into the source/drain regions ofan MOS device in accordance with the present invention.

DETAILED DESCRIPTION OF THE INVENTION

FIGS. 1A-1C show a semiconductor processing sequence which results inintroduction of a germanium-rich layer into the channel of an MOStransistor structure near the interfacial region to enhance the mobilityof minority carriers.

As shown in FIG. 1A, a layer of photoresist 10 is deposited andpatterned by conventional methods to define a channel region 12 in asilicon substrate 14. Germanium, at a dose of 2×10¹⁶ Ge/cm² and anenergy of 40 KEV, is then implanted into the channel region 12.

As shown in FIG. 1B, after the photoresist 10 has been stripped, a wetoxidation step is performed at 900° C. for 30-60 minutes to grow oxidelayer 16 on the silicon and creating a germanium-rich layer 18 at theinterfacial region of the silicon substrate 14. (Those skilled in theart will appreciate that while FIG. 1B shows a distinct difference inthickness in the differential oxide layer 16 overlying thegermanium-rich layer 18 for illustrative purposes, the actual thicknessof the oxide overlying the germanium-rich layer 18 will be only severalhundred Angstroms greater than the remainder of the oxide layer 16.) Thelength of the wet oxidation step should be sufficient to achieve agermanium concentration of at least 95% in the layer 18. However, theoxidation step should be as short as possible, since, at a point,germanium diffusion will begin to occur from the germanium-rich layer 18to the substrate silicon 14.

As shown in FIG. 1C, the oxide layer 16 is then stripped and subsequenttreatment of the silicon substrate 14 is essentially in accordance withstandard integrated circuit fabrication techniques to define an MOStransistor structure have a source region 20, drain region 22, and gateregion 24 overlying the channel region 12.

As disclosed by O. W. Holland et al, "Novel Oxidation Process inGermanium Implanted Silicon and its Effect on Oxidation Kinetics",Applied Physics Letter 51:520 (1987), the use of wet oxidation stepswill involve enhanced oxidation rates because of the presence ofgermanium in the silicon substrate 14. This enhancement permits shorteroxidation times at lower temperatures which reduces undesired dopantdiffusion.

While the effect of germanium on the dry oxidation rate has not beencarefully examined, it is expected that some enhancement of theoxidation rate will occur due to the presence of a germanium layer,since barriers to bond breaking are lower than in pure silicon.

As is well known, the approximate ratio of drift mobilities forelectrons and holes in intrinsic germanium versus intrinsic siliconequals

    μ.sub.n (Ge)/μ.sub.n (Si)≃2.6,

    μ.sub.p (Ge)/μ.sub.p (Si)≃4.2.

In the presence of impurities, the drift mobility ratio is changed. Forexample, in the presence of an impurity concentration of 10¹⁷ cm⁻³,

    μ.sub.n (Ge)/μ.sub.n (Si)≃3.7,

    μ.sub.p (Ge)/μ.sub.p (Si)≃3.0.

These ratios show that, while the presence of dopants will affect themobilities, drift mobilities remain significantly higher in germanium.Consequently, inversion in the channel for either N-channel or P-channelMOS transistors will result in significantly increased drift mobilitiesof the minority carriers due to the presence of the germanium layer 18.

FIGS. 2A and 2B show a semiconductor processing sequence in which theabove-described properties of germanium in silicon are utilized toprovide lower contact resistance in the source and drain regions of MOStransistors.

As shown in FIG. 2A, a layer of photoresist is deposited and patternedaccording to conventional methods to define surface regions 30 and 32 inwhich respective source and drain regions 34 and 36 are formed byintroduction of appropriate dopants. Germanium is then implanted inaccordance with the dosage and implant energy parameters cited above.

As shown in FIG. 2B, following a wet oxidation step which results in theformation of a germanium-rich layer at the interfacial region, the oxideis stripped and processing proceeds in a conventional manner to definean MOS transistor structure that includes source region 34, drain region36 and gate electrode 38.

The concentration of germanium in the germanium-rich interfacial regionis not so critical as in the case of the "channel region" embodimentdescribed above, but should be at least 70%.

The advantages of the presence of a thin germanium layer in thesource/drain regions at the contact interface are at least twofold.First, additional wet oxidation can be used to grow a source/drain oxidewhich, when etched, produces a very smooth interface. This surfacepreparation enables greater contact area with a metal plug. Moreover,the germanium is a low resistivity material. Second, the germanium layerprovides silicide contact resistance lowering. Since silicon diffusesrapidly through germanium, it is expected that thesilicide/germanium-silicon interface will be smoother than if nogermanium layer were present. Detrimental effects that might occur ifdopant diffusion from the silicon into the forming silicide wereextensive (increased contact resistance) would be compensated for by thelow resistivity germanium. All of this leads to enhanced contactconductance in the source/drain regions.

As shown in FIGS. 3A-3B, formation of a layer of silicon-germanium alloyof a desired germanium purity, to enhance channel mobility and/or lowercontact resistance as described above, may also be achieved without wetoxidation utilizing molecular beam epitaxy (MBE).

Referring to FIG. 3A, in the context of source and drain regions 40 and42, respectively, one possible MBE technique would entail masking thesource and drain regions 40, 42 with photoresist 44 and then notchingthese regions to a desired depth (e.g. 0.25 microns) utilizing a quickplasma etch. An epitaxial silicon-germanium alloy 46 is then depositedin the notch by any desired conventional MBE technique to obtain adesired Si:Ge mole-fraction ratio (Si_(1-x) Ge_(x)). The Si_(1-x) Ge_(x)epitaxial layer 46 is then etched back to obtain a desired surfaceprofile, as shown in FIG. 3B. The MOS device structure is then completedin the conventional manner by forming gate oxide 48 and overlying gateelectrode 50. As in the case of the wet oxidation procedure describedabove, the germanium concentration in the alloy 46 should be at least70%.

Those skilled in the art will appreciate that the MBE techniquedescribed above for enhancing contact resistance in source/drain regionsis also applicable to enhancement of drift mobility in the channelregion of MOS devices. As with the wet oxidation technique describedabove for accomplishing this end, the germanium concentration in thegermanium-rich interfacial layer of the channel should be at least 95%.

It should be understood that various alternatives to the embodiment ofthe invention described herein may be employed in practicing theinvention. It is intended that the following claims define the scope ofthe invention and that methods within the scope of these claims andtheir equivalents be covered thereby.

What is claimed is:
 1. A method of providing lower contact resistance inthe source ad drain regions of an MOS transistor, the method comprisingthe sequential steps of:(a) defining source and drain regions in asilicon substrate, the source and drain regions being spaced apart todefine a channel region therebetween; (b) after defining the source anddrain regions forming an epitaxial layer of silicon-germanium alloy atthe surface of the source and drain regions; and (c) after forming anepitaxial layer forming an MOS transistor structure comprising thesource and drain regions and a gate electrode overlying the channelregion and separated therefrom by a layer of dielectric material.
 2. Amethod as in claim 1 wherein the silicon-germanium alloy comprises atleast 70% germanium.